The present invention relates generally to memory circuits and, more particularly to a method of and apparatus for writing to and reading from a memory device using current drivers and current sensing logic.
An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM allows a memory circuit to execute both read and write operations on its memory cells. A typical example of a RAM device is a static random access memory (SRAM).
A standard SRAM cell 10 is shown in FIG. 1. The cell 10 consists of four transistors 14, 16, 18, 20 that form a bistable flip-flop and two control or access transistors 12, 22. The access transistors 12, 22 have their gate terminals connected to a word select line WS (also known as a word line). The first access transistor 12 is coupled between a first bit line DBIT and a first node A. The second access transistor 22 is coupled between a second bit line DBIT_N (typically the complement of the first bit line DBIT) and a second node B.
Data is written or stored into the cell 10 with either a high potential at node A and a low potential at node B, or a low potential at node A and a high potential at node B. This means that two stable states are available, which are defined as either a logic xe2x80x9c1xe2x80x9d or a logic xe2x80x9c0xe2x80x9d. The configuration of the four transistors 14, 16, 18, 20 (i.e., flip-flop) is such that the potentials at the two nodes A, B are retained as long as power is supplied to the cell 10. Thus, unlike other RAM devices (e.g., DRAM), the SRAM cell 10 does not need to be periodically refreshed to retain its contents.
The logic state of the SRAM cell 10 is read by sensing the differential voltage developed on the bit line pair comprised of the two bit lines DBIT, DBIT_N. When the word line WS is selected, the access transistors 12, 22 are turned on, which allows access to the cell""s 10 contents via the bit lines DBIT, DBIT_N. In most applications, the SRAM cell 10 is embedded in an array of similar cells. The typical array is organized into a plurality of rows and columns, with rows corresponding to word lines (e.g., WS) and columns corresponding to the bit lines (e.g., DBIT, DBIT_N). To read data stored in the SRAM array, row and column addresses are used to access the desired memory cell (via the WS, DBIT and DBIT_N). That is, a particular address within the SRAM array is accessed.
Another form of memory is the content addressable memory (CAM) device. A CAM is a memory device that accelerates any application requiring fast searches of a database, list, or pattern, such as in database machines, image or voice recognition, or computer and communication networks. CAMs provide benefits over other memory search algorithms by simultaneously comparing the desired information (i.e., data being stored within a given memory location) against the entire list of pre-stored entries. As a result of their unique searching algorithm, CAM devices are frequently employed in network equipment, particularly routers and switches, computer systems and other devices that require rapid content searching.
In order to perform a memory search in the above-identified manner, CAMs are organized differently than other memory devices (e.g., SRAM). As set forth above, in an SRAM device, during a memory access, the user supplies an address and reads into or gets back the data at the specified address. In a CAM, however, data is stored in locations in a somewhat random fashion. The locations can be selected by an address bus, or the data can be written into the first empty memory location. Every location has a pair of status bits that keep track of whether the location is storing valid information in it or is empty and available for writing.
Once information is stored in a memory location, it is found by comparing every bit in memory with data placed in a match detection circuit. When the content stored in the CAM memory location does not match the data placed in the match detection circuit, the CAM device returns a no match indication. When the content stored in the CAM memory location matches the data placed in the match detection circuit, the CAM device returns a match indication. In addition, the CAM may return the identification of the address location in which the desired data is stored. Thus, with a CAM, the user supplies the data and gets back the address if there is a match found in memory.
FIG. 2 illustrates a typical CAM cell 30, which for the most part comprises an SRAM cell 10. The CAM cell 30 is a static memory device and is sometimes referred to as a static CAM cell. Additional transistors 32, 34, 36, 38 are used to report the result of the matching function performed by the CAM 30. The matching function is performed by an exclusive-NOR operation, so that a match is only indicated if both the stored bit and a corresponding comparand bit (i.e., bit to be searched for) have the same state. The four additional transistors 32, 34, 36, 38 are used to perform the exclusive NOR (xe2x80x9cXNORxe2x80x9d) and match line MLINE driving operations (discussed below) and will be referred to herein as the XNOR transistors 32, 34, 36, 38.
The first XNOR transistor 32 has its gate coupled to the complementary match bit line (MBIT_N) and is coupled between the second XNOR transistor 34 and a ground potential. The second XNOR transistor 34 has its gate coupled to the first node A and is coupled between the first XNOR transistor 32 and a match line MLINE. The fourth XNOR transistor 38 has its gate coupled to the match bit line (MBIT) and is coupled between the third XNOR transistor 36 and a ground potential. The third XNOR transistor 36 has its gate coupled to the second node B and is coupled between the fourth XNOR transistor 38 and the match line MLINE. The match bit line MBIT will contain the value of the comparand while the complementary match bit line MBIT_N will contain the complementary value of the comparand.
For writing and reading, the CAM cell 30 is operated as an SRAM cell. That is, the differential bit lines DBIT, DBIT_N are used to latch data into the cell 30 when writing, while the differential on these bit lines are sensed (via sense amplifiers) during reading. For comparing, the match line MLINE is typically precharged to a high potential (e.g., VDD). The XNOR transistors 32, 34, 36, 38 compare the internally stored state of the cell 30 to the state of the comparand (via match bit lines MBIT, MBIT_N). If the states do not match, the match line MLINE is pulled down to the ground potential via the XNOR transistors 32, 34, 36, 38 to indicate the mismatch. The match line MLINE is fed to an encoder that determines whether any matches exists, whether more than one match exists, and which location is considered the highest priority.
In SRAM and CAM devices, the bit lines DBIT, DBIT_N traverse the whole depth of the devices. Being long lines, heavily loaded with capacitance, read and write operations utilizing the bit lines DBIT, DBIT_N take a significant amount of time to complete and consume a large percentage of the power dissipated in the memory device. It is desirable to increase the speed of read and write operations and reduce the amount of power consumed during the read and write operations performed in SRAM and CAM devices.
The present invention provides a static memory device having reduced power consumption during read and write operations.
The present invention provides a static memory device having increased read and write operation speeds.
The above and other features and advantages are achieved by a static memory device that utilizes differential current bit line drivers to write information into the device""s memory cells, and differential current sensing read amplifiers to read information from the cells. The drivers and amplifiers operate using limited differential current. The use of limited differential current, as opposed to voltages, reduces the power consumed by the device and increases the speed of read and write operations.